StarVision PRO Training for Qualcomm

Date March 3 2022

Time 11.00 am PST - 12.00 pm PST

Location EDA Direct

Location Address Online Training

Overview:

Complex SoC (System on Chip) development requires you to bring 3rd party IP, RTL, SPICE netlist, and Post layout netlist files together. Join this session to learn how to efficiently and very quickly integrate digital and analog blocks to build a system without extra coding.

**Please Note: If you have registered for a past event, document or video, just Log in with your email. (Otherwise you will see a registration error comment and will have to log in again).

What you will learn:

  • Visualize: Render schematics on the fly from any RTL, Spice, CDL, Calibre and SPEF/DSPF netlists
  • Tracing: Navigate and trace signals easily between digital and analog domains. No need to ascend and descend into cell views
  • Prune: Prune and save critical timing paths/fragments of the design as Verilog or Spice to speed up simulation
  • ERC Checks: Calculate Pin to Pin Resistance, Find decoupling capacitors, Reduce/Filter Parasitics on the net and many more
  • Incomplete design: Can read incomplete RTL designs unlike simulators and synthesis tools
  • Netlist Reduction: Remove clock tree buffers for easier visualization
  • Flat/Hierarchy: Create hierarchy by grouping transistors. Flatten the design or recreate hierarchy on the fly.
  • Bookmark files: Files can be bookmarked and opened/debugged by a remote engineer
  • Export Schematics: To Cadence Virtuoso
  • Documentation: Generate design statistics & reports: Instance & primitive counts. Copy/Paste schematics & signal path into powerpoint for design reviews
  • TCL API: Access to full design database through tcl scripts. Examples include identifying differences in netlists during ECOs.
  • Capacity & Performance: Extremely memory efficient to handle today’s full chip netlists.
  • ESD Checks: identify missing ESD protection schemes quickly at the netlist level, and save on simulation time by identifying ESD issues statically.

Who should attend: 

  • IC Design and Layout Engineers
  • CAD Engineers
  • IP Procurement Teams
  • SOC Integration Teams

By subscribing, you will receive EDA Direct account and email newsletter membership.
Please see our other great events, whitepapers & videos that you can log into directly with your email, after registering.

analog spice + digital + parasitics

 


About Us

Customer service is our religion. We have an unsurpassed, proven ability to understand the issues you face, help you select the right tools, and support you like no other.
  • 4701 Patrick Henry Drive #1301 Santa Clara, CA 95054
  • sales@edadirect.com
  • 408-496-5890
  • 408-684-8854
  • Other Offices : Austin, TX | Irvine, CA | San Diego, CA

Ready to get started

We strive to become your technology partner and appreciate the opportunity to win your business. Let’s work together to ensure that your company is on the path to success.