Category: Design visualization and analysis
Vendor: Concept Engineering
StarVision™ PRO provides engineers with the ability to quickly and easily understand and debug mixed-mode designs and to integrate IP building blocks into their complex SoCs and ICs.
RTL-Level, Gate-Level and SPICE-Level in one Integrated Debugging and Visualization Tool – Due to the increasing use of building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, parasitic) as well as with different design languages and netlist formats. To support this challenge, Concept Engineering developed StarVision PRO, an integrated debugging cockpit for mixed-signal and digital design that makes analysis and debugging of complex SoC and IC designs easy and more transparent.
- For debugging full chip before Tape out
- For SOC integration teams
- For engineers who want RTL to Parasitic debugging
- Must have tool for CAD teams due to support of most industry standard formats
#schematic #SchematicAnalyzer #verilogSchematicViewer #VHDLSchematicViewer #NetlistAnalyzer #NetlistViewer #NetlistVerification
