Category: Design visualization and analysis
Vendor: Concept Engineering
Using RTL or Verilog or EDIF netlists, these tools fits seamlessly into any design environment. The power of the underlying algorithms allows schematics to be created on the fly and the intuitive GUI lets the designer search for critical paths, for paths between specific components or for specific areas in the design. These can be bookmarked for future use, or cross-probed between different design views.
- For RTL ASIC and FPGA design and verification engineers
- For DFT engineers
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