System on a Chip ( SOC) Integration Debug Flow Webinar 1.30pm PDT

Date May 17 2022

Time 1.30 pm PDT - 2.30 pm PDT

Location EDA Direct

Location Address Online Webinar

Overview:

Complex SoC (system on chip) development requires you to bring 3rd party IP, RTL, SPICE netlist, and Post layout netlist files together. Join this webinar to learn how to efficiently and very quickly integrate digital and analog blocks to build a system without extra coding. 

* Please Note: If you have registered for a past event, document or video, just Log in with your email. (Please do not try to re-register as you will see a registration error comment).

What you will learn:

  • VISUALIZE: Netlist of multiple formats. We start off by showing the user ways on how to read in simple circuits of various formats and dialects such as RTL, Spice and extracted DSPF and SPEF.  Sample files include reading examples of a PDK showing how quickly and easily decisions can be made on which device to use or not use in an SOC. We then read in larger circuits and show methods on how to perform netlist reductions, trace critical design paths and cross probe between source code and netlist. 
  • NETLIST REDUCTION: Reduce circuit complexity. Remove clock tree buffers, resistors and capacitors for easier circuit visualization and tracing.
  • TRACE, PRUNE and CROSS-PROBING: Here, methods are introduced on how to trace specific areas of the design, perform netlist pruning of critical design paths/fragments for reuse as IP or for critical path partial simulation. Drag & drop selected components/nets between all design views (schematic, logic cone and source code view and simulation data) to cross probe and shorten debug time, especially during tape-out for full chip debug.
  • Tcl API: Extend functionality to match project needs by interfacing with the open database through scripts. Throughout the presentation, we’ll show users a selection of scripts developed to help perform: Clock Domain Analysis, Annotating text based reports such as timing reports on the generated netlist, Creating documentation and reports, Performing a diff between two netlists, Performing Electrical Rule Checks, ERC and showing design statistics graphically to name a few. 
  • CLOCK DOMAIN ANALYZER: Visualize and detect different clock domains and clock trees in the design.
  • TIMING CLOSURE: Read timing reports and annotate timing data and see critical paths.
  • DOCUMENT: Generate design statistics & reports for archiving or for regulatory compliance such as ISO 26262 required for autonomous vehicles. 
  • IDENTIFY DIFFERENCES IN SCHEMATICS: Extend the capabilities of the tool to identify differences between designs and visually see the differences.
  • ELECTROSTATIC DISCHARGE CHECKS: Verify the robustness of your electrostatic discharge (ESD) protection strategy in your design is essential to ensure sufficiently-sized devices and interconnects are where they need to be for circuit robustness.

Who should attend: 

  •         Analog and Digital Design, DFT and Verification Engineers / Managers
  •         CAD Engineers / Managers
  •         IP Procurement Teams
  •         FPGA Engineers
  •         SOC Integrators
  •         Front End engineers
By subscribing, you will receive EDA Direct account and email newsletter membership. Please see our other great eventswhitepapers & videos that you can log into directly with your email, after registering.

Feel free to share with your colleagues.

sv_webinar screen shot


About Us

Customer service is our religion. We have an unsurpassed, proven ability to understand the issues you face, help you select the right tools, and support you like no other.
  • 4701 Patrick Henry Drive #1301 Santa Clara, CA 95054
  • sales@edadirect.com
  • 408-496-5890
  • 408-684-8854
  • Other Offices : Austin, TX | Irvine, CA | San Diego, CA

Ready to get started

We strive to become your technology partner and appreciate the opportunity to win your business. Let’s work together to ensure that your company is on the path to success.