Fast, Accurate Analog/Mixed-Signal Analysis and Debug Webinar

Date April 2 2020

Time 11.00 am PST - 12.00 pm PST

Location EDA Direct

Location Address Online Webinar


Complex SoC (system on chip) development requires you to bring 3rd party IP, RTL, SPICE netlist, and Post layout netlist files together.

Join this webinar to learn how to efficiently and very quickly integrate digital and analog blocks to build a system without extra coding.


What you will learn:

  • Visualize: Render schematics on the fly from any RTL, Spice, CDL, Calibre and SPEF/DSPF netlists
  • Tracing: Navigate and trace signals easily between digital and analog domains. No need to ascend and descend into cell views
  • Prune: Prune and save critical timing paths/fragments of the design as Verilog or Spice to speed up simulation
  • ERC Checks: Calculate Pin to Pin Resistance, Find decoupling capacitors, Reduce/Filter Parasitics on the net and many more
  • Incomplete design: Can read incomplete RTL designs unlike simulators and synthesis tools
  • Netlist Reduction: Remove clock tree buffers for easier visualization
  • Flat/Hierarchy: Create hierarchy by grouping transistors. Flatten the design or recreate hierarchy on the fly.
  • Bookmark files: Files can be bookmarked and opened/debugged by a remote engineer
  • Export Schematics: To Cadence Virtuoso
  • Documentation: Generate design statistics & reports: Instance & primitive counts. Copy/Paste schematics & signal path into powerpoint for design reviews
  • TCL API: Access to full design database through tcl scripts. Examples include identifying differences in netlists during ECOs.
  • Capacity & Performance: Extremely memory efficient to handle today’s full chip netlists.

Who should attend: 

  • IC Design and Layout Engineers
  • CAD Engineers
  • IP Procurement Teams
  • SOC Integration Teams
This Event is over. Get the recording here

analog spice + digital + parasitics

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