SOS from ClioSoft is the leading design data collaboration platform for SoC design teams. It is integrated into analog design tools from all major electronic design automation (EDA) vendors, enabling design teams to build, collaborate and manage their designs efficiently from the EDA tool cockpit. Using SOS, designers can effectively manage the different versions of schematic, layout and other associated cell views, review the differences in schematic or layout and share their design data with other designers located either locally or across multiple sites.
SOS – Virtuoso
SOS – Custom Compiler
SOS – Pyxis
SOS – ADS
Visual Design Diff (VDD)
ClioSoft’s Visual Design Diff (VDD) gives users the power to quickly compare two versions of a schematic or layout by graphically highlighting the differences directly in the design editor. VDD has the option to ignore cosmetic changes so mere rearrangement or rerouting of wires will not be flagged. Users can also choose to invoke a hierarchical diff where all differences for the entire design hierarchy below the selected view will be flagged.
Cadence Virtuoso 6.x (OpenAccess)
Cadence Virtuoso 5.x (CDBA)
Supported View Types:
SOS Digital is built on the powerful SOS7 design platform from ClioSoft, to meet the unique requirements of semiconductor design teams. The requirements of SoC designs – design complexity, different EDA tools from numerous vendors, extremely large binary tool databases and a complex design flow – is quite different from the needs of the software teams, and cannot be met by the tools commonly used in the software industry. With its distributed and fault tolerant architecture, SOS7 from ClioSoft enables design teams to collaborate across geographically dispersed design centers without compromising on either performance, security or robustness. It provides a flexible platform, which can be easily customized to meet the requirements of any design flow. Design teams can quickly create custom handshakes to establish their own hand-off protocols for notification or set triggers to run scripts to validate design hand-offs.
For hardware digital engineering teams
Reference and Reuse IP
Branching and Merging
High performance Remote Site collaboration support
Flexible search order to create customized workspace
Integrated with bug tracking system like Jira, Trac, Bugzilla and Fusion forge
StarVision™ PRO provides engineers with the ability to quickly and easily understand and debug mixed-mode designs and to integrate IP building blocks into their complex SoCs and ICs.
RTL-Level, Gate-Level and SPICE-Level in one Integrated Debugging and Visualization Tool – Due to the increasing use of building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, parasitic) as well as with different design languages and netlist formats. To support this challenge, Concept Engineering developed StarVision PRO, an integrated debugging cockpit for mixed-signal and digital design that makes analysis and debugging of complex SoC and IC designs easy and more transparent.
For debugging full chip before Tape out
For SOC integration teams
For engineers who want RTL to Parasitic debugging
Must have tool for CAD teams due to support of most industry standard formats
Spice files are difficult to read. SpiceVision automatically generates circuit schematics on screen and speeds up debugging and project development. The SpiceVision product family helps to solve design problems in: Digital Circuits, Mixed-Signal ASICs, Analog Circuits, Printed Circuit Boards and MEMS.
For Analog and Mixed Signal SOC engineers
For CAD team supporting design teams
For Layout engineers
Supports SPEF and DSPF parasitic visualization and analysis
Using RTL or Verilog or EDIF netlists, these tools fits seamlessly into any design environment. The power of the underlying algorithms allows schematics to be created on the fly and the intuitive GUI lets the designer search for critical paths, for paths between specific components or for specific areas in the design. These can be bookmarked for future use, or cross-probed between different design views.
For RTL ASIC and FPGA design and verification engineers
For DFT engineers
Schematic Integrity Analysis
Schematic integrity analysis enables full inspection of all nets on a schematic using pre-defined checks and an extensive intelligent model component library. Schematic analysis saves design teams hundreds of hours of visual inspection and lab debug time by automating 100+ proprietary checks for each net within a schematic. These checks execute rapidly prior to your schematic freeze milestone, such that layout may commence with highest confidence of first-pass success.
Schematic integrity analysis is performed in parallel with design schematic capture. It can also be performed on electronic designs after they have been released into the market to improve the quality of the electronic design, to increase yield, and to decrease product returns.
Schematic Integrity Analysis
Full multi-board and backplane interface verification
Driver/receiver technology matching
Power/ground/open collector/drain shorts
Poor design practice checks (e.g. using pull-ups, pull downs when needed…)
Nets missing driver/receiver
Pin voltage parametric verification for maximum, minimum, and logic thresholds
Only PADS® can provide engineers and small teams with a product creation platform optimized for component selection, signal and power integrity, electronics cooling, form and fit, PCB layout, and manufacturing.
Analyze signal integrity issues early in the design cycle to eliminate costly re-spins. HyperLynx® Signal Integrity (SI) generates fast, easy and accurate signal integrity analysis in PCB systems design. HyperLynx SI helps engineers efficiently manage rule exploration, definition and validation, ensuring that engineering intent is fully achieved. The software is tightly integrated from schematic design through final layout verification. It can quickly and accurately resolve typical high-speed design effects including over/undershoot, ringing, crosstalk and timing.
Signal Integrity Analysis
Pre/Post-Layout Time/Frequency-Domain Analysis
SPICE/S-Param Model Extraction and IBIS-AMI Support
The Questa® Verification Solution transforms verification, dramatically increasing verification productivity and managing resources more efficiently built on several powerful technologies and tightly integrated with Veloce® emulation Questa answers the challenges of increasingly complex SoCs.
Electronics cooling software from the leader in electronics thermal analysis. The powerful FloTHERM® suite of 3D computational fluid dynamics (CFD) software predicts airflow and heat transfer, in and around electronic equipment. FloTHERM delivers right-by-design products that save design time and reduce the need for physical prototyping from components and boards to complete systems and data centers.
Thermal Integrity Analysis
Expedite System Model Creation with SmallPart Library
Robust Industry-Standard CFD Engine
Automated Parametric Design Optimization
MCAD Imports (SolidWorks, STEP, IGES, Catia,…)
ECAD Import (Allegro, Expedition, PADS, Zuken,…)
Powerful Result Visualization w/Particle Flow Analysis
Accurately model power distribution networks and noise propagation mechanisms throughout the PCB design process. Identify potential power integrity distribution issues that can interfere with board design logic, and investigate and validate solutions in an easy-to-use, “what-if” environment with HyperLynx® PI. This intuitive tool gives any member of your design team the ability to quickly and accurately analyze power integrity, without the usual steep learning curve of most power analysis products.
Design team access to these sophisticated power integrity capabilities will help companies reduce prototype spins, shorten time to market, and allow engineers to develop more reliable products.
Power Integrity Analysis
DC-Drop Analysis On Plane/Trace Copper Pours
AC-Decoupling Analysis to Control PDN Impedances
Optimizing PDN Strategies using Plane Noise Analysis
Today’s designs rely heavily on a growing variety of complex industry standard interfaces that must be verified to ensure IP interoperability and system behavior. Mentor’s verification IP (VIP) improves quality and reduces schedule times by building Mentor’s protocol and methodology expertise into a library of reusable components that support many industry standard interfaces. This frees up engineering resources from having to spend time developing BFMs, verification components, or VIP themselves, enabling them to focus on the unique and high-value aspects of their design.
FloEFD is a full-featured 3D computational fluid dynamics analysis solution built into major MCAD systems such as Creo, CATIA V5, Siemens NX and SolidWorks. It tightly integrates with Inventor and SolidEdge.
Embedded in the leading CAD systems for concurrent design simulation
Easy-to-use with full-featured 3D fluid flow and heat transfer analysis
Numerous engineering models such as porous media, PCB and LED model
Electronics cooling module for detailed thermal modeling of electronic models
HVAC module for detailed modeling of HVAC applications, including comfort parameters
Automated Cartesian immersed boundary mesher
Advanced module for more detailed modeling of advanced flow features such as combustion and hypersonic flow
LED module for more accurate thermal modeling of LEDs and other lighting sources with LED thermal model and Monte Carlo radiation model
Up to 75% faster simulation cycle with CAD embedded Concurrent CFD
Valor NPI products combine capabilities of design for manufacture (DFM) and new product introduction (NPI) to ensure smooth transition from PCB design to fabrication, assembly and test from any PCB design environment. More than 700 manufacturing rules can be applied concurrently throughout the design flow to reduce revisions and costly re-spins at the manufacturing level.
Automatic DFM analysis for new design versions with pinpointed manufacturing problems directly in the layout environment
BOM, AVL, and component analysis for assembly and test processes
Documentation and manufacturing-level outputs at the board or panel level
Tight integration with layout, with changes dynamically reflected in manufacturing drawings
Unified mixed language simulation engine for ease of use and performance
Native support of Verilog, SystemVerilog for design, and VHDL, for effective verification of sophisticated design environments
Fast time-to-debug, easy to use, multi-language debug environment
Advanced code coverage and analysis tools for fast time to coverage closure
Interactive and Post-Sim Debug available so same debug environment used for both
Powerful Waveform Compare for easy analysis of differences and bugs
Advanced code coverage and analysis tools for fast time to coverage closure
Unified Coverage Database with complete interactive and HTML reporting and processing for understanding and debugging coverage throughout your project
Xpedition® Enterprise from Mentor Graphics is the industry’s most innovative PCB design flow, providing integration from system design definition to manufacturing execution. Its unique, patented technologies can reduce design cycles by 50 percent or more while significantly improving overall quality and resource efficiency. Improve PCB design efficiency and time-to-market with rigid-flex PCB design.
MunEDA SPT Schematic Porting Tool is the first commercially available solution for automated circuit migration and design porting between different process technologies. It can be used to migrate existing IP from a source PDK to a target PDK saving lots of migration time and effort.
Customer proven and automated flow for Design Migration & IP Porting of existing IP between different process technologies
Fast Schematic Migration with MunEDA SPT Schematic Porting Tool
Save Time and Efforts
Make designer’s life more convenient and results reliable
Circuit Analysis and Verification
Circuit analysis & verification tools include numerous features and functionalities for enhanced circuit design analysis, diagnosis and verification. This contains single and multi-testbench capabilities, multi-simulator-analysis, scripting support by multi-script-languages, sensitivity analysis, nominal and performance diagnosis, constraint management, design space exploration, PVT corner analysis, Statistical Yield Analysis, Monte Carlo Analysis, High- and Ultra-High-Sigma-Analysis (3 to 9 sigma and more), mismatch analysis, reliability analysis, area analysis, power analysis and many more.
Circuit Sizing and Optimization
WiCked includes the best-in-class optimization and sizing tools on the market including functionality for constraint fulfilment and feasibility optimization, performance optimization, power optimization, area optimization, yield optimization, reliability optimization and many more. WiCkeD’s optimization tools have been successfully used in hundreds of design and tape-out projects within the last decade in all kind process technology.