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Lunch & Learn: Parasitic Debugging in Complex Design – How Easy?

May 17, 2018
12:00 PM - 1:00 PM (PDT)
EDA Direct Office
4701 Patrick Henry Dr, Suite #13, Santa Clara, CA
When we talk about parasitic, we talk about post layout design further expanded in terms of electrical components such as resistances and capacitance's. In the semiconductor design environment where multiple parts of a design from different sources are assembled together into highly complex, high density SoC, imagine how complex it would be to debug that design at parasitic level.
We will demonstrate methodologies and tools to help locate the problem area’s in your SPICE/Parasitic designs. With great navigation and cross-probing, simplify a portion of the design view at a desired level (e.g., modify symbols, move up to gate or down to transistor level, remove RC etc.) to understand the problem, review Spice netlist and fix at any level as appropriate.

Who Should Attend
  • Analog Designer
  • Analog Layout Engineer
  • Mixed Signal Layout Engineer
  • Mixed Signal Design Manager
  • RTL Design & Verification Engineer's

What you will learn:
  • Automatic Schematic generation from Spice, DSPF, LVS Spice, Spectre
  • Quickly debug post layout parasitic spice or SPEF netlist with or without RC
  • Full chip netlist tracing (top level integration and block level)
  • Obtain detailed 'insight' to optimize for Speed and Power Consumption
  • Analyze results of LVS runs and use the automatically generated SV PRO schematics from extracted SPICE netlists with RC network
  • Overlay DSPF data to debug the design
  • Very fast and can load extremely large netlists