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Expert Clock Domain Crossing (CDC) & FIFO Design Techniques using SystemVerilog

March 20, 2018
10:00 AM - 5:00 PM (PDT)
EDA Direct
4701 Patrick Henry Dr Suite #13, Santa Clara, CA
Please note this class is held in SANTA CLARA, CA, USA.
Class is conducted by Cliff Cummings. Cliff Cummings is the only Verilog & SystemVerilog Trainer who helped develop every IEEE & Accellera Verilog, Verilog Synthesis and SystemVerilog Standard.
 
Duration: 1 Day 60% Lecture, 40% Lab
Cost: $650 per student
 
Upon completion of this course, students will:   Write efficient synthesizable SystemVerilog RTL models
  • includes six different FSM coding styles
  • includes multi-clock and FIFO design techniques
 
Overview
Sunburst Design - Expert Clock Domain Crossing & FIFO Design Techniques using SystemVerilog is a 1-day intensive course that focuses on some of the most advanced design techniques using SystemVerilog. This SystemVerilog training was developed and is frequently updated by the renowned SystemVerilog guru and IEEE SystemVerilog committee member, Cliff Cummings. Cliff has presented at numerous SystemVerilog seminars and training classes world wide, including the 2003-2004 SystemVerilog NOW! Seminars, the 2010 ModelSim SystemVerilog Assertion Based Verification Seminars, and multiple Verification Academy DAC seminars. This course covers advanced multi-clock design techniques not available anywhere else and not commonly taught at the University level.
 
Target Audience Sunburst Design - Expert Clock Domain Crossing & FIFO Design Techniques using SystemVerilog is intended for design engineers who require advanced multi-clock design knowledge.
 
Prerequisites (mandatory) This is a very advanced design techniques class that assumes engineers already have a good working knowledge of the Verilog & SystemVerilog languages. This course assumes that students have a practical working knowledge of SystemVerilog RTL Design.
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