More Info: SystemVerilog Assertions (SVA) Training
SystemVerilog Assertions (SVA) Training
March 21, 2018
9:00 AM - 4:00 PM (PDT)
4701 Patrick Henry Dr, Suite #13, Santa Clara, CA
Please Note: This class is held in Santa Clara, CA, USA.
Class is conducted by Cliff Cummings. Cliff Cummings is the only Verilog & SystemVerilog Trainer who helped develop every IEEE & Accellera Verilog, Verilog Synthesis and SystemVerilog Standard.
Duration: 1 Day
50% Lecture, 50% Lab
Cost: $650 per student
In recent years Cliff has been called on to conduct SystemVerilog Assertion (SVA) training for companies that had previously taken multi-day SVA training, not because the training they received was bad, but because the training they received was too much and their engineering teams had a hard time remembering all of the SVA options and syntax possibilities. The problem is that engineers use SVA sporadically for a few months on one project, then they might go many months before they need to use it again.
Learn concise, syntax error-avoidance coding styles to make design and verification engineers productive and make them eager to use assertions in RTL designs. Experience has shown that engineers can become efficient after 2-3 hours of SVA lecture and 2-3 hours of SVA lab work. In this course, engineers will be trained to:
Use bindfiles to add assertions to a design
Use long, descriptive labels to:
document the assertions
accelerate debugging using waveform displays
Use simple macros to:
efficiently add concise assertions
reduce assertion coding efforts
reduce assertion syntax errors
Use concurrent assertions but avoid immediate assertions
Use |-> ##1 implications instead of |=> implications
Gain valuable SVA writing and debugging experience through lab work where engineers are asked to debug a 1‐clock synchronous FIFO design with 8 subtle bugs.
Sunburst Design - SystemVerilog Assertions (SVA) Training is intended for design and verification engineers who require efficient and productive SVA knowledge to help rapidly identify and correct design bugs.
This is an advanced SystemVerilog class that assumes engineers already have a good working knowledge of the SystemVerilog language.