More Info: PCIe System Verification Using Questa Verification IP
PCIe System Verification Using Questa Verification IP
September 20, 2017
10:00 AM - 3:00 PM (PDT)
4701 Patrick Henry Dr Suite #13
Verification of IP blocks, subsystems and complete SOCs is a major challenge for the industry today. Verification teams are using multiple tools and methodologies to achieve design functionality. One very common and valuable tool is Verification IP. Mentor Graphics VIP provides comprehensive protocol test stimulus and coverage checking that allows you to easily deploy advanced verification methodologies. Verification planning, constrained random and functional coverage methodologies are all included for standard bus protocols, in this case PCIe.
Join EDA Direct and Mentor Graphics on this webinar focusing on PCIe which is one of the most commonly used protocols and also one of the most complicated. Using Mentor VIP you will learn how to stimulate your DUT at a higher level of abstraction, and use Questa transaction level debug environment with Mentor VIP for maximum debug productivity of PCIe.
Mentor VIP leverages SystemVerilog, and some knowledge of this or UVM/OVM is recommended. Many tools and techniques exist to help with this problem including languages, verification methodologies and EDA tools. The industry is standardizing on SystemVerilog to enable modern verification techniques such as Assertions, Constrained Random and Functional Coverage. Methodologies such as OVM/UVM provide the necessary infrastructures and enable re-use across projects.
On the design side we are seeing increased use of industry standard interfaces to enable the reuse of design IP necessary to compete in the marketplace. Rigorous testing of design interfaces may be needed and standard verification IP can be created that can be reused across projects. As such, Questa VIP can be used to leverage advanced verification methodologies like verification planning, constrained random and functional coverage.
What You Will Learn
How to simulate your design at a higher level of abstraction
How to use TLM (Transaction Level Modeling) to increase visibility at the system level
How to use Assertions, Constrained Random, and Functional Coverage effectively
How to integrate Verification IP (VIP) into your OVM/UVM environment