More Info: Lunch and Learn: High Speed Signal Integrity Ghz
Lunch and Learn: High Speed Signal Integrity Ghz
May 23, 2018
12:00 PM - 2:00 PM (PDT)
EDA Direct Office
4701 Patrick Henry Dr, Suite #13, Santa Clara, CA
HyperLynx can be used to address Signal Integrity issues in your FPGA designs. Learn how advanced simulation technology, packaged within an easy-to-use environment, can dramatically improve your time-to-results, giving you more opportunity to innovate while meeting deadlines and cost goals.
Advances in process and SERDES technologies create fundamental challenges in PCB design and signal integrity analysis for high-speed interfaces such as DDR2/3/4 and multi-gigabit serial channels. For the Electrical Engineer designers, the effects of overshoots, undershoots, jitters, losses, crosstalks, and BER (Bit Error Rate) need to be analyzed. For the Layout designers, differential path matchings, termination placements, and layers as well as impedance selections are crucial in ensuring a quality PCB design. Higher edge rates can also create fundamental Electromagnetic Interference (EMI) issues in today’s designs.
In this lunch and learn we will analyze multi-gigabit Serial IO designs both in pre-layout and post-layout. This allows you to simulate topologies, device technologies, detail eye-diagram analysis, advanced via modeling, and crosstalk analysis to ensure the quality of your board designs.
What you will learn:
How to analyze Overshoot/Undershoot issues and effective Termination strategies.
How Skin-effect and Dielectric losses can negatively affect your operating regions.
How to create, extract, analyze via structures using the new full 3D Field Solver for signal losses and radiation effects.
How to use the IBIS-AMI models to analyze eye diagrams, bathtub curves, and use worse-case PRBS to check for channel linearity of your high-speed SERDES channels.
How to effectively control the Pre-emphasis and equalization parameters to minimize ISI
How S-parameters can be used in HyperLynx to analyze board-level interconnects inclusive of S-parameter viewings and extractions.
How to analyze including advanced DDR2/3/4, and SERDES architectures
How to create 3D model in BoardSim for analysis in HyperLynx 3D
Hyperlynx can be deployed in any PCB Design flow, including Cadence Allegro, Mentor PADS, Expedition, or Altium