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Irvine: Modern FPGA/ASIC Verification Methodologies Workshop

April 26, 2018
10:00 AM - 3:00 PM (PDT)
Mentor Graphics Irvine Office
18301 Von Karman Avenue Suite 760 Irvine, California, 92612

  Overview
FPGA vendors continue to push the boundaries creating innovative new ways for FPGA users to efficiently design today's increasingly complex FPGAs. This created a widening gap between design abstraction and verification of these FPGAs in which traditional verification approaches come up short. Users implementing complex FPGAs such as Stratix or Virtex also face similar challenges. In addition, many of today’s FPG designs requires safety related verification. These challenges shift the balance in verification methodologies as more FPGA users want and need to adopt modern verification practices in order to be competitive but don't always know where to start or find the cost/risk too great.  

Join EDA Direct in this workshop to learn about themes in the FPGA industry that are pushing the need for advanced verification, understand how other FPGA users in industry are adapting to this and see how taking a new look at your verification methodologies can help you build higher quality, on-time products enabling you to be more competitive in today’s evolving FPG market. The methodologies covered include Code and Functional Coverage, Assertions, Automated Testbench Generation, Automated Formal Verification, and Clock Domain Crossing checks. Hands on labs will reinforce the discussed methodologies.  

What You Will Learn
  • What is Code and Functional Coverage and how to collect Code Coverage data
  • How to write SystemVerilog Functional Coverage and Assertions
  • How to write Assertions in PSL and how to use OVL
  • How to create a new UVM test environment using the UVM Framework code generator
  • Automated Testbench Generation with UVM Framework, QVIP, and Verification Run Manager
  • How to write a test sequence and run and debug a testcase within the GUI
  • What is Formal Verification, and how to setup, run, and debug with Questa AutoCheck/Covercheck
  • What is metastability and the challenges in detecting these in simulation
  • How to setup, run and debug with Questa CDC
  • How to simulate and debug with metastability models

Who Should Attend
  • FPGA/ASIC Design Engineer
  • Verification Engineer

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