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Electrical Rule Checks For Complex and High Speed PCB Designs

April 4, 2018
10:10 AM - 11:00 AM (PDT)
Online Webinar via RingCentral/Zoom
Join EDA Direct webinar to learn how eDRC (Electrical Design Rule Checking) can be used to optimize the electrical quality of your PCB designs before fabrication.

Electrical rules checking accelerates the electrical sign-off process by allowing engineers to identify violations that can affect the design integrity and performance of the board. This includes a core set of electrical rule checks, and offers extensive customizability. It uses the physical board layout geometries and performs advanced geometrical operations on these objects to detect any electrical Signal Integrity, EMI, and Power Integrity violations.

Issues such as traces crossing voids and traces changing reference planes can be quickly identified even on the largest designs. Integrated electrical DRC technology enables engineers to be confident that their PCB designs are electrically correct before hand-off to manufacturing. These checks can be done in minutes to reveal issues that otherwise maybe missed in board layout. This is done without having to do extensive SI/PI analysis to detect issues.

Input Requirement
  • Customers provide the post-layout board in the following formats: Allegro (*.a_b, *.brd), ODB++, Altium (*.hyp file output), Zuken (*.paf, *.bsf, *.pcf), PADS (*.brd, *.cce), Expedition (*.pcb), BoardStation (*.prt)

    Analysis Performed
    • EMI Checks (13 rules)
      • IO Coupling, Net Crossing Gaps, VIA stub lengths, Exposed Lengths, Metal Islands, Edge Rate To Period, Edge Shield, Filter Placement, IC’s Over Split, Net Near Plane Edge, Signal Supply, Vertical Reference Plane Change, Return Path.
    • Signal Integrity (SI) Checks (21 rules)
      • Acute Angle, Crosstalk Coupling, Delay and Length Matching, Diff Impedance, Edge Rate, Many VIAs, Diff Pairs, Diff Pair Pad Parasitic Capacitance, Diff Pair Spacing, Diff Pair Phase Matching, Diff Pair Symmetry, Guard Trace, Impedance, Long Nets, Long Stubs, Termination Check, Fly-By Topology, Relative Delay and Length Matching, Star Topology, T-Fork Topology, VIA to VIA Isolation
    • Power Integrity (PI) Checks (6 rules)
      • Decoupling Capacitor Placement, Decoupling Capacitor Coverage, Decoupling VIA Location, Decoupling Capacitor order, PDN VIA Count, Pwr/Gnd widths
    • Additional Checks (8 rules)
      • 2D Creepage Distance, 3D Clearance, 3D Voltage Clearance, Breakout and trace Integrity, Clamshell Topology Diff Pair Impedance, Clamshell Topology Impedance, Clamshell Topology Length, Creepage for Safety Standards.


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