More Info: High Speed Signal and Power Integrity Analysis
High Speed Signal and Power Integrity Analysis
April 18, 2018
10:00 AM - 11:00 AM (PDT)
Online Webinar via RingCentral/Zoom
Joint EDA Direct to learn about Signal Integrity and Power Integrity Analysis for today’s high speed FPGA designs. Learn the effects of overshoot, undershoot, ringing, losses, crosstalk, and BER (Bit Error Rate) on transmission lines. Layout constraints such as differential length matchings, termination placements, layer stackup affecting impedances are crucial in ensuring a quality PCB design. Systems containing backplane structures with >26Gb rates require extensive analysis to ensure high throughput and low BER. New capabilities in SERDES analysis (CTLE, COM, PAM-4) have been developed for analyzing 200-400Gb systems. Modern FPGA devices such as the Xilinx UltraScale and others incorporate advanced SERDES and high-speed interfaces such as DDR4, etc.. that simplify system implementation but can create challenges in SI/PI analysis.
In this webinar, we will help you learn and perform SI/PI Analysis. Using the Xilinx VCU108 Development Board we will look at Termination, Crosstalk, and DDR4 Timing Analysis. In addition, we will review Eye Diagram analysis, Frequency-Domain Analysis, and advanced 3D via modeling. Power Integrity Analysis will also be discussed covering excessive DC Drop, High Current Density, and AC Decoupling to control PDN impedance.
What You Will Learn
How to plan Board Stackup to control Impedance and trace modeling.
How to analyze Overshoot/Undershoot/Crosstalk issues and effective Termination strategies.
How to extract S-Param models and analyze via structures using full 3D Field Solver.
How to use the IBIS-AMI models to analyze eye diagrams, bathtub curves, and use worse-case PRBS to check for channel linearity of your high-speed SERDES channels.
How to use CTLE, COM, and PAM-4 for Eye diagram analysis.
How to analyze DDR4 memory subsystems
How to analyze PDN structures for potential Power Integrity issues