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Lunch & Learn: Eliminate Schematic Design Errors with Automated Verification

April 12, 2018
12:00 PM - 1:30 PM (PDT)
EDA Direct Office
4701 Patrick Henry Dr, Suite #13, Santa Clara, CA
lunchandlearn

Overview
Today’s complex designs no longer allow for manual schematic review and verification.  Many designs incorporate ASICs and high pin-count FPGAs (with reconfigurable IO Standards) pose challenge in verifying electrical connectivity between devices.   Manual inspections can be time consuming and error prone to minimize connectivity problems that can lead to board respin and product failures in the field.

Join EDA Direct for a Lunch and Learn session on how to fully automate schematic verification in your PCB designs.  Schematic integrity analysis enables full inspection of all nets on a schematic using pre-defined checks and an extensive intelligent model component library. With Xpedition Valydate you will be able to save design teams hundreds of hours of visual inspection and lab debug time. In this workshop we will highlight our schematic checker that can operate with any PCB EDA vendor and highlight how you may use the checks in-built into Xpedition validate to improve quality of electronic design, increase yield and decrease product returns.

In this Lunch and Learn session we will introduce how automation can be setup to verify these checks as well as learn how to write custom checks for designs using FPGAs and ASICs.

What You Will Learn
  •  How to create custom models for new component.
  • How to use the multi-milion part library that is cloud-based to constantly have access to the latest models added.
  • How to run schematic checks for the following
    • Pin voltage parametric verification
    • Bus flip errors (MSB-to-LSB, Tx/Rx errors)
    • Symbol mismatch to datasheet
    • Power/Gnd/Open collector/dran shorts and plane connection verification
    • Poor design practice checks (pull-ups, pull downs, termination, etc..)
    • Component power checks
    • Differential pins verification
    • Nets missing driver/receiver, floating, and unconnected.
    • Pextract end-to-end nets to S-Parameter models for loss analysis

Who Should Attend
  • FPGA/ASIC Design Engineers
  • PCB Designers
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