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Eliminate PCB Schematic Design Errors and save re-spins

July 19, 2018
10:00 AM - 11:00 AM (PDT)
Online Webinar
Valydate
Overview
Today’s complex designs no longer allow for manual schematic review and verification.  Many designs incorporate ASICs and high pin-count FPGAs (with reconfigurable IO Standards) pose challenge in verifying electrical connectivity between devices.   Manual inspections can be time consuming and error prone to minimize connectivity problems that can lead to board respin and product failures in the field.
Join EDA Direct for a webinar on how to fully automate schematic verification in your PCB designs.  Schematic integrity analysis enables full inspection of all nets on a schematic using pre-defined checks and an extensive intelligent model component library.
What You Will Learn
  •  How to create custom models for new component.
  • How to use the multi-milion part library that is cloud-based to constantly have access to the latest models added.
  • How to run schematic checks for the following
    • Pin voltage parametric verification
    • Bus flip errors (MSB-to-LSB, Tx/Rx errors)
    • Symbol mismatch to datasheet
    • Power/Gnd/Open collector/dran shorts and plane connection verification
    • Poor design practice checks (pull-ups, pull downs, termination, etc..)
    • Component power checks
    • Differential pins verification
    • Nets missing driver/receiver, floating, and unconnected.
    • Extract end-to-end nets to S-Parameter models for loss analysis
Who Should Attend
  • FPGA/ASIC Design Engineers
  • PCB Designers
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