We cordially invite you to attend this webinar how to efficiently debug your Analog designs from Pre to Post Layout, in one intuitive environment.
Most transistor-level circuit designers time is spent doing debugging, looking at waveforms, reading tables of text results, and trying to understand why the circuit is acting differently than intended. In order to really understand what is happening with your newest IP block or re-used IP, you need some automation help in looking at the netlist or interconnect in a visual way.
visualize any SPICE netlist so that you can quickly traverse it.
We'll present how to locate an exact problem area using great navigation and cross-probing, simplifying a portion of the design viewing at a desired level (e.g. modify symbols, move up to gate or down to transistor level, remove RC etc.) to understand the problem, review Spice netlist and fix at any level as appropriate.
The tools are versatile enough supporting most of the industry standard formats that include Verilog, SV, VHDL, EDIF, Spice, HSpice, Spectre, Calibre, CDL, DSPF, RSPF, SPEF, Eldo, PSpice and IBIS.
What you will learn:
Understand the topology and function of the circuit without having schematics
Automatic Schematic generation from Spice, DSPF, LVS Spice, Spectre
Traverse hierarchy, search nets/instances very fast
Cross probing with GDS for highlighting nets
Verify connectivity especially for multi fanin and fanout nets
ERC Checking: Floating input and output nets, heavy connected nets, etc.