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How to Design and Analyze Your Next High-Speed Memory Subsystem with DDRx

March 8, 2018
10:00 AM - 11:00 AM (PST)
Online Webinar via RingCentral/Zoom
HyperLynx DDRx
Join EDA Direct for a webinar of the latest DDRx (DDR3/4) memory subsystem and how to design with it on the PCB.
Designing with DDRx poses challenges such as constraint definition, timing alignment for clock and strobe signals for DDRx designs. We will also look at LPDDRx interface for low power applications. DDR4 is an entirely new architecture with higher bandwidth, lower power consumption, and higher density. To achieve these results its architecture and implementation changed drastically compare to older mentor architectures (ie. DDR3, DDR4). These, however, pose additional challenges in board designs and at the higher clock rates (up to 2.133GHz for LPDDR4) board design and routing can be very challenging.
In this webinar we will review the new DDRx/LPDDRx architectures, what’s required for functional operation, and how it can be simulated on your PCB board. Based on the simulation results, you can focus on optimizing trace routing, board stackup, component placements, connectors, terminations, as well as other tradeoffs to maximize the performance of your design.
What you will learn:
  • DDRx topology planning
  • New DDRx wizard assisting with Timing Analysis of DDR3/DDR4
  • Minimizing Crosstalk effects on your board around the memory subsystem
  • Signal Integrity (SI) and Power Integrity (PI) co-simulation techniques and results.