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Lunch & Learn: Mixed-Signal Design Debugging Made Easy!

March 28, 2018
12:00 PM - 1:30 AM (PDT)
EDA Direct
4701 Patrick Henry Dr
Unified Digital and Mixed-Signal Debug


We cordially invite you to attend this lunch and learn how to quickly debug your designs.
A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals.
Considering today’s large SoC designs with multiple IPs, it’s imperative that effective debugging tools with easy and quick visualization, navigation, annotations etc. are a must for designers to make right decisions during the course of design.

Attend this Lunch&Learn to learn how Mixed-Signal Debug can be made easy. We'll cover methods your semiconductor design can be visualized with its parts at Spice, Gate or RTL level either in schematic or in its source code format. We will show efficient debug methods from Concept, to Post-layout design.

Who Should Attend

  • Analog Designer
  • Analog Layout Engineer
  • Mixed Signal Layout Engineer
  • Mixed Signal Design Manager
  • RTL Design & Verification Engineer's

What you will learn:

VISUALIZE: Render schematics on the fly for VHDL/Verilog/Spice level netlists to understand function of design easily. Supported formats include Verilog, VHDL, SystemVerilog, Liberty, SPICE, HSPICE, Spectre, Calibre, CDL, DSPF, SPEF
PRUNE: Extract, navigate and save critical timing paths/fragments of design as Verilog/Spice/SPEF netlists with the ‘cone view’, for reuse as IP or external use in partial simulation
CLOCK TREE ANALYZER: Visualize and detect different clock domains in the design. Configure Clock cells and also verify the clock domain crossing.
CROSS-PROBE: Drag & drop selected components/nets between all design views (schematic, logic cone, Parasitic window and source code view) to cross probe and shorten debug time, especially during tape-out for full chip debug
PARASITIC: Visualize and analyze parasitic networks (Post layout formats: DSPF, RSPF, SPEF) and create SPICE netlists for critical path simulation
NETLIST REDUCTION: Instantly turn off/on parasitic structures in SPICE circuits for better comprehension of CMOS function
SKILL EXPORT: Export schematics and schematic fragments into Cadence Virtuoso Schematic for further optimization and debugging using in-build SKILL exporter and Symbol utility package.
ERC CHECK: Verify/debug connectivity especially for multi fan-in and fan-out nets by identifying floating input and output nets, heavy connected nets, etc.
HIERARCHY Vs FLAT: Ability to convert a Flat netlist into hierarchy and a hierarchical netlist into Flat using our extensive API tcl support
SEARCH & CONE: Using "Search and Cone" Feature to find that one transistor/component/module/net/port/gate in large flattened Netlist.
SOC OR MIXED SIGNAL DESIGN: Visualize, Debug and Analyze the RTL, GATE and SPICE Design in one cockpit!
DOCUMENT: Generate design statistics & reports: Instance & primitive counts
TCL API: Extend functionality of StarVision to match project needs by interfacing with the open database through tcl scripts and in batch mode