Join EDA Direct webinar to learn how eDRC (Electrical Design Rule Checking), PI DC Drop/Current Density, and DDRx Analysis can be used to optimize the performance of your PCB designs
Electrical rules checking accelerates the electrical sign-off process by allowing engineers to identify violations that can affect the design integrity and performance of the board. This includes a core set of electrical rule checks, and offers extensive customizability. It uses the physical board layout geometries and performs advanced geometrical operations on these objects to detect any electrical Signal Integrity, EMI, and Power Integrity violations. Issues such as traces crossing voids and traces changing reference planes can be quickly identified even on the largest designs. Integrated electrical DRC technology enables engineers to be confident that their PCB designs are electrically correct before hand-off to manufacturing. These checks can be done in minutes to reveal issues that otherwise maybe missed in board layout. This is done without having to do extensive SI/PI analysis to detect issues.
For Power Integrity, designs today have multiple IO standards requiring multiple voltage rails (3.3, 2.5, 1.8, 1.5, 1.2, 1.1, 1.0, 0.9, etc..) creating complexities in implementing power plane structures in the PCBs. Components onboard can demand high current surges during high activities and clean power references are required for proper board functionality. The VRMs (Voltage Regulator Module) cannot regulate efficiently during these high switching activities and excessive voltage drop issues can exist for brief periods that can induce sporadic system errors. Also, insufficient in power trace widths can create “choke” points with localizing high current density areas which can cause trace delamination over time. Identify these issues help minimize board failures in the field, increase system reliability, and reduce layout costs.
DDR memory has become commonplace across the spectrum of electronics designs and is now found in the mainstream markets. Analyzing these memory subsystems in addition to following best design practices can guarantee proper operation at the optimum speeds. Proper selection of terminations, stackups, trace spacings, trace impedances and ODT (On Die Termination) selections are required to optimize DDRx signaling and timing margins at high speed. This allows both the Electrical as well as layout engineers to quickly identify and solve signal integrity (SI) and timing issues specific to DDRx designs before release to production. What You Will Learn
How to import PCB layout from Altium, Allegro, Zuken, Mentor, etc..
Analyze power plane cutouts for excessive DC drops that can create intermittent IC switching issues and identify neck-down areas with high current densities
Investigate optimum VRM (Voltage Regulator Module) selections and placements